Integrated circuit memory devices are widely used in consumer and commercial applications. As the operational speed of Central Processing Units (CPU) continues to increase, it also may be desirable to increase the operational speed of integrated circuit memory devices. Accordingly, synchronous Dynamic Random Access Memories (DRAM) have been developed that operate in synchronization with a system clock. Moreover, multi-bank integrated circuit memory devices also have been developed in which a plurality of banks of memory cells are provided. The plurality of banks of memory cells may operate in an interleaved manner to increase the operational speed of the multi-bank integrated circuit memory devices.
As the integration density of integrated circuit memory devices continues to increase and the operational speed increases, it is known to increase the number of banks to thereby increase the effective bandwidth of the multi-bank integrated circuit memory devices. For example, a 16-Mb DRAM may include two banks, a 64-Mb DRAM may include two or four banks, a 256-Mb DRAM may include four banks and other high-speed integrated circuit memory devices such as Rambus integrated circuit memory devices may include 16 or more banks.
Prefetch schemes also may be used in synchronous DRAMs to operate at high speeds. In particular, in a synchronous DRAM having a prefetch scheme, an external address or command may be input for every two cycles of the system clock. Moreover, at least two Column Select Lines (CSL) that are selected by at least two column addresses, may be enabled for two cycles of the system clock. This operation is often called a 2N rule or a 2-bit prefetch.
In multi-bank integrated circuit memory devices, the respective banks may include independent row decoders and column decoders that operate independently. When the number of banks increases and a prefetch scheme is used, the banks may be arranged in a plurality of rows and columns of banks. Each bank generally receives its own row address information so as to be independently controlled. Accordingly, as the number of banks increases, the number of row address signal lines may also increase and the size of the integrated circuit may also increase undesirably.
It is also known to divide each bank of memory cells into two sub-banks of memory cells that are arranged in a plurality of rows and columns of sub-banks of memory cells. For example, in a publication by Saeki et al., entitled "A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay", IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, November 1996, pages 1656-1665, a multi-bank integrated circuit memory device is described including four banks, each of which consists of two sub-banks for lower byte data and upper byte data. As illustrated in FIG. 1 of the Saeki et al. publication, the sub-banks are arranged in two rows and four columns with the two sub-banks of each bank being in the same row. Unfortunately, as the number of banks continues to increase, the number of signal lines that transmit row address information also may continue to increase and the size of the multi-bank integrated circuit memory device also may increase undesirably.